ORION 2
EXTRACODE
PROGRAMS
10th June 1964
This memorandum is a revised version of 102 Computer Memorandum No.B.31, which should be deleted.
The effects of the special orders and other special facilities provided for use by the extracode programs, are described below. For explanation of how the orders are used, see the extracode programs and their accompanying documentation.
When the "Extracode Mode" flip-flop is set or the "Extracode" handkey is feeling depressed, then the functions giving special extracode orders have their special effects. On all other occasions they have their normal effects as described in the Orion manual.
The 87 instruction does much the same in and out of Extracode mode, but has a few special effects in.
Extracode mode is entered (i.e. the "Extracode" flip-flop is set and various information is placed in the store as described below) when the following orders are obeyed:
102, 103 ) these instructions or instruction
125, 126 ) pairs are carried out entirely by
140/142, 141/142 ) extracode
140/154, 140/155 )
division orders, 40-45, when the quotient appears to be out of range. Extracode detects and deals with certain cases in which the quotient is not in fact out of range.
101, 95. Certain combinations of operands require help from Extracode.
156 when in monitoring or engineers mode.
Extracode mode is left by the 87 or 23E orders (action as described below).
Lockout and reservation testing are suppressed;
the abandonment address (W) is not updated when in extracode mode;
the special extracode orders are effective;
if one of the reasons for entering extracode, listed above, occurs, death will occur ("Enter Extracode" micro-program). This shouldn't happen, and death has been made to occur so as to detect faults causing it.
entry to the timesharer is prevented. Thus, once an extracode program is entered it is guaranteed not to be interrupted until it is finished. (Hesitations, of course, are not affected by Extracode mode).
the datum is not taken from the lower reservation address, but is a built-in address, 512 in fact.
Note 20E, for example, means the effects of the function 20 when obeyed in Extracode mode.
87 Some special effects when obeyed in Extracode mode.
20E Load lockout address and set lockout tester into action.
21E Read back lockout address and set lockout tester out of action.
22E Transmit on the peripherals Bus Out, and receive information back on the peripherals Bus In.
23E Leave an Extracode Order and set indicators.
24E Character conversion order.
25E First column-row conversion order.
26E Second column-row conversion order.
27E Line "normalization" for the buffered Anelex line printer.
102E First card read partial conversion order.
103E Second card read partial conversion order.
105E Character transfer order for paper tape transfers.
106E As 105E but terminating on a NL char.
107E Set the abandonment address.
125E Test Lockout and Reservation Region for Input Transfer (i.e. strong test).
127E Test Lockout and. Reservation Region for Output Transfers (i.e. weak test).
140E Line image preparation for unbuffered Anelex printer.
Information will be placed in registers 512 to 516.
512 contains X at the l.s. end. Bit 47 = 1 if in monitoring or engineers mode.
513 contains the seven F-bits as follows: the l.s. two F-bits in the two m.s. bits, the next four F-bits in the four l.s. bits, and the m.s. F-bit in position 28. Also, bit 23 will be 1 if the order is 3-address.
514 contains Y (24 bits) at the l.s. end. Bit 47 = 1 if floating pt operations are unrounded. Bit 46 = 1 if monitoring on overflow.
515 contains X or Z (both 15 bits) at the l.s. end, depending on whether the instruction is 2 or 3-address respectively. Bit 46 = 1 if monitoring on floating point overflow. Bit 47 = 1 for the second of a 140, 141, 142, 154, 155 pair.
516 contains J at the l.s. end. Bit 47 = 1 if OVR is set on entry to Extracode.
The first order obeyed is in 517.
87 In Extracode mode the 87 order has the following effects in addition to its normal effects:
reset the "Extracode" flip-flop
update the abandonment address (to X + ym) except at the end of a 140 or 141 instruction.
leave the normal testing for abandonment of a successful jump instruction until after the abandonment address has been updated as in (ii).
The address at the l.s. end of x. is put onto the flip-flop register specified by Y, according to the following interpretation of Y:
(a) the four least significant bits give the number of the lockout or reservation tester: numbers 1-7 are lockout testers corresponding to fast peripheral controls with number one less; 0 is the reservation tester;
(b) the fifth and sixth bits specify the address within the tester by:
0 0 the lower address
0 1 the upper address
1 0 the current address (magnetic tape only)
1 1 strong/weak from x0, except for the reservation tester for which strong/weak is set from x45 when loading the upper address.
The lockout tester concerned is set into action if the upper address is being loaded, i.e. if the sixth and fifth bits are 0 1.
The locked out regions include the lower and upper lockout addresses, and the reservation tester permits use of the lower and upper reservation addresses.
The lower reservation address is 0 mod 64, i.e. its least significant six bits are zero, and if an address not 0 mod 64 is loaded onto the lower reservation address its least significant six bits are lost.
This order is the same as 20E except that the address is put into x, and if Y6 = 0 the lockout tester concerned is set out of action. The contents of the lockout or reservation address register concerned is not changed.
Transmit a General Request, Monitor with the least significant 8 information channels set from the least significant 8 bits of X, the 9th channel is forced to be 1 (meaning "Monitor"), and the other channels 0.
Receive the information on the twelve least significant channels of the peripheral Bus In, in the two digit times following the General Request, putting the first dollop in the least significant quarter of z and the second dollop in the next quarter, bits 12-23 (if there is only one dollop's worth of reply, the second dollop will be a repeat of the first).
If the order is 3-address a Control Dollop is transmitted, with the information channels set from the least significant 12 bits of Y.
If X0 = 1 (i.e. l.s. bit of X) set "Program Fail"
X1 = 1 set "Peripheral Incident"
X2 = 1 set "Peripheral Lockout"
X3 = 1 set "Requirement Set"
X4 = 1 reset "Peripheral Incident"
When the x bits are zero, the state of the corresponding flip-flop is not changed.
If X5 = 1, leave Extracode (i.e. reset the Extracode flip-flop) and abandon the order setting OVR according to the sign bit of y (This will make use of the link left in 516 on entry to Extracode)
The 23E instruction is only used with X5 = 1 when the order being carried out by Extracode has to be abandoned. On all other occasions the 87 must be used. This is because the 23E does not deal with J and W properly when the order has been successful.
Convert the eight characters of x according to the conversion table starting at Y, and put the result in accumulator Z (3 addr) or X (2 addr). The table is 8 words long. Calling the characters of x xi, the conversion process is to put the xith character of the table into zi
Convert the 6-bit column ordered words in X, X+1. X+2, to 24-bit row elements in Y, Y+2, Y+4. Thus the ms bit of X will go in the ms bit position of Y, and the first 24 bits of Y will be obtained by taking every 6th bit of X, X+1, X+2 starting with the most significant. The 25th bit of Y will be the second bit of X; and so on.
Convert the 24-bit row elements in X and X+1 into two 48-bit row elements in Y and Y+1.
Thus:
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ms X ls |
ms X+1 ls |
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Transfer character field starting at ms end of Y+1 to field starting at ms end of X, removing tabulate character pairs, and putting subsequent characters in their correct position. If a NL. or PT character is encountered, it and the following character are placed in the ls 12 bits of Z, and the transfer is terminated.
The word in X is converted using the mask in Y as described below, and the result is placed in Z. OVR nay be set.
x is assumed to be an unconverted word read in from a card as described in CS290; e.g. ba1., ba2, ba3, ba4, bb1, bb2, bb3, bb4
y is assumed to be a mask consisting of 1s in the lower curtate (i.e. not upper curtate) of the ms column only (e.g. ba1, bb1).
z will have in it the digit parts of the four v characters, as described in CS290, and the ms bit of each u character will contain a 1 if the corresponding lower curtate, as defined by the mask, contains two or more holes, except that
the v characters are put at the ms and the u characters at the ls end of z;
if there were no holes in the lower curtate of a column, and the only hole or holes in the column are in the 10 or 11 position, then their contribution to v will not be formed, but Overflow will be set.
if more than one hole in lower curtate, v is cleared, 1 is inserted in u, and overflow is set.
in the case of Bull, the mask should not include the 10 or 11 positions even though they are nominally in the lower curtate. The presence of a 10 or 11 digit punching is expected to be detected by a separate collating order, with appropriate action if there is one.
Conditions (b) and (d) really come to saying that those cases in which 10 and 11 contribute to v are not dealt with, but in the case of (b) OVR is set to indicate that this has happened.
Transfer z characters from the field starting at xch , (i.e. from the character xc in x. For example if x = 010 ...... N, then the first character is bits 30-35 of register N) to the field starting at ych. The remaining characters of the last destination word involved are made zero.
The same as 105E except that:-
the order is terminated if a NL character is encountered in the source field. In this case the NL is the last character transferred.
the number of characters transferred is written to Z.
Set the abandonment address, W, to be Y.
This order is used to help with large input transfers from slow peripherals. See the extracode programs and their write up for a full explanation of its use.
The region from x to y inclusive is tested for lockout or reservation failure, and as a result information is written to Z. If either a lockout or a reservation failure occurs, then bit 47 of z is made 1. Also, if a lockout failure occurs, then the address of a word which is locked out is found and stored in Z. Otherwise Z is left clear. For this order to work, the top 24 bits of x and y must be the same.
As for 125E except weak test instead of strong.
Place bits for the third of a line image starting at Y for the 8 characters of x, and with the insertion bit placed in Z initially and placed there shifted down 8 places at the end of the order.
The order is used repeatedly to prepare the following image of a line from a string of 120 (approx) characters. Each character has three words representing it with 1s in those positions where the character is to be printed. The first character on the print wheel is represented in this way in Y, Y+1 and Y+2, the next in Y+3 to Y+5, etc. The ms bit of Y corresponds to the leftmost print position of the page.
The hesitation control does not clear the image when printing the line, so it needs clearing before preparing the next line image.
A 102 Computer Memorandum, No.B.13, "Method of Sending Information to the Anelex Printer", explains the use of this order.
The word in X is taken and using it and the mask in Y, check bits are generated for the ms two bits of each v character and mixed into the appropriate places in z, and z is cyclically shifted 24 places.
the word, z is the same as for the 102E order.
the mask is assumed to contain 1s in the 1 to 9 positions of the ms
column (e.g. ba1, bb1 ) only, i.e. it is
O3 13 O18 16 O18.
z has the v bits inserted according to the specification in CS290.
M.D.Bigg